1. Field of the Invention
The present invention relates to a method and apparatus for processing synchronously transferred data, and, more particularly, to a data processing method and a SCSI protocol controller suitable for data transfer using SCSI (Small Computer System Interface).
2. Description of the Related Art
Interfaces which can transfer a vast amount of data between a personal computer and peripheral devices at a fast transfer rate are essential in the multimedia environment. A system interface called "SCSI" is one of such interfaces. SCSI defines two kinds of data transfer systems, synchronous transfer and asynchronous transfer. The synchronous transfer which is excellent in accomplishing a fast transfer rate can be adapted to the SCSI-3 standard of the next generation of computers.
A SCSI protocol controller constituted by a single large scale semiconductor integrated circuit (LSI) chip has an internal memory device (e.g., a data register such as FIFO). FIG. 1 presents a timing chart illustrating the write timing of the data register which operates in response to a request (REQ) signal or an acknowledge (ACK) signal in synchronous transfer.
The ACK and REQ signals are control signals for transferring data supplied from the microprocessor unit or DMA controller in a personal computer. Eight-bit parallel data is transferred within a period where the ACK signal falls to the Low level, then rises to the Hi level and falls to the Low level again.
For example, the SCSI protocol controller holds data supplied from a SCSI bus in the setup period, and then sets a sync write signal SNWR to the Hi level in response to the Low level ACK signal and the rising of an internal clock signal CLK. This sync write signal SNWR falls to the Low level in response to the next rising of the clock signal CLK.
When the sync write signal SNWR rises, the protocol controller writes data into the internal memory device (data register) in accordance with an address in an address counter incorporated in this protocol controller. The address counter increments the address by "1" in response to the Low level sync write signal SNWR and the rising of the first internal clock signal CLK output after writing. As a result, the write address for the next data is designated.
Next, after holding the next data, the protocol controller sets the sync write signal SNWR to the Hi level again in response to the Low level ACK signal and the internal clock signal CLK. The protocol controller writes new eight-bit parallel data into the internal memory device in accordance with the address in the address counter.
The data transfer rate in the synchronous transfer is determined by the frequency of the ACK (REQ) signal. In other words, an ACK (REQ) signal having a relatively high frequency increases the data transfer rate. The timings for the write signal and the address change in the address counter at the time of writing data into the internal memory device are determined based on the internal clock signal CLK in consideration of the setup time and hold time. The internal clock is generated in such a way that several clock pulses are generated for one period of the ACK (REQ) signal. In FIG. 1, four clock pulses are produced for one period of the ACK (REQ) signal. This means that the protocol controller produces the internal clock CLK whose frequency is four times the frequency of the ACK (REQ) signal.
Increasing the frequency of the ACK (REQ) signal to make data transfer faster requires that the frequency of the internal clock signal CLK be increased even moreso. This raising of the frequency of the internal clock signal CLK increases the number of operations of each circuit element. This increases the consumed power of the protocol controller. A considerable amount of both work and time are needed to design a fast circuit for a single chip SCSI protocol controller which conforms to the SCSI-3 (Fast-20) standard of the next generation that permits fast data transfer.